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Scientific Reports volume 12, Article number: 21389 (2022) Cite this article
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The HLS of digital filters is a complex optimization task in electronic design automation that increases the level of abstraction for designing and scheming digital circuits. The complexity of this issue attracting the interest of the researcher and solution of this issue is a big challenge for the researcher. The scientists are trying to present the various most powerful methods for this issue, but keep in mind these methods could be trapped in the complex space of this problem due to own weaknesses. Due to shortcomings of these methods, we are trying to design a new framework with the mixture of the phases of the powerful approaches for high level synthesis of digital filters in this work. This modification has been done by merging the chimp optimizer with sine cosine functions. The sine cosine phases helped in enhancing the exploitation phase of the chimp optimizer and also ignored the local optima in the search area during the searching of new shortest paths. The algorithms have been applied on 23-standard test suites and 14-digital filters for verifying the performance of the algorithms. Experimental results of single and multi-objective functions have been compared in terms of best score, best maxima, average, standard deviation, execution time, occupied area and speed respectively. Furthermore, by analyzing the effectiveness of the proposed algorithm with the recent algorithms for the HLS digital filters design, this can be concluded that the proposed method dominates the other two methods in HLS digital filters design. Another prominent feature of the proposed system in addition to the stated enhancement, is its rapid runtime, lowest delay, occupied area and lowest power in achieving an appropriate response. This could greatly reduce the cost of systems with broad dimensions while increasing the design speed.
High-level synthesis (HLS) is a hot topic and a design process in which a high-level, functional description of a design is automatically compiled into an register transfer level setup that meets some user-defined design constraints. In re-timing, any difficult optimization problem can be alienated into independent sub-problems. If any problem or function have divided into ((m-1)) flip-flops, in that decreasing the overall time by these factor (m). Generally this process is apply to obtain synchronous circuits (SYC). And re-timing method is used to enhanced the speed of the SYC without changing the latency and functionality¹. A re-timing method can also be generalized to locate non-critical gates that can be operated with low supply voltages to reduce overall system power consumption. The various re-timing strategies have developed by the researchers in the literature for the issues of power consumption such as^2,3,4 respectively. In Ref.⁵, have developed a new framework for retiming and for the digital filters the digital signal processing blocks based evolutionary computation process. During this strategy takes the inputs form the user in the form of data flow graphs or matrices or obtains all optimal solutions in the search domain.
In addition, the high level of synthesis of digital filtering is a big challenge for the engineers. In this issue researchers have solved various complacence’s of the power consumption in the terms of maximized frequency and reducing area. Last few decades, various recent MA’s are applied for tackling of these kinds of issues. And for the demand of the future more robust algorithms are developing, so that these can be used to fulfil the future requirements. For highlighting the important of this work we are discussing more by the following some references.
Digital filter can be categorized into two main groups: Finite Impulse Response (FIR)⁶ and Infinite Impulse Response (IIR)⁷. Filters⁸, are the major crucial systems in most electronic and computing machines. Filtering aims to extract information about the most relevant interesting signals, either by extracting frequency components or by separating desired components from unwanted signals or eliminating noise. As per view of the mathematical, the designing of the digital filters according to a specified criterion, can be formulated as an optimization function where need to find the best suites specifications. Thus, the various robust stochastic algorithms during the last few decades has developed the different kinds of metaheuristic algorithms (MHAs). These are sophisticated MA’s, they are often a better alternative to traditional nature inspired algorithms, giving an excellent trade off amid the computing time and optimal solution’s quality, particularly for complex optimization functions or large dimension issues. Generally, the metaheuristic algorithm can be divided into different phases as per sources of inspiration⁹: (1) natural phenomena (NP) methods that imitate the principles of physics and chemistry. (2) Evolutionary methods that follow the natural evolution processes found in nature; and (3) swarm intelligence (SI) methods, including population-based algorithms that mimic the social behavior of insects or animals. In particular, Chimp Optimizer¹⁰, is a new population based method that has already started attracting attention. In this study we are trying to present the novel hybrid method with the mixture of two powerful algorithms such as ChOA with Sine Cosine, it is called SChoA. These powerful features of two methods play an important role for trapping the best solutions in the global search space. The sine cosine features helped in enhancing the exploitation phase of the chimp optimizer and also ignored the local optima in the search area during the searching of new shortest paths. The main objective of this study is to introduce the powerful method for considering the high level synthesis of the complex dimension digital filters. The experimental numerical and statistical outcomes show that the proposed method performance is superior to other well-known MHAs in the literature. In summary, the main contributions of this paper are:
A novel improved algorithm called SChoA method that includes features from Chimp and sine cosine functions is proposed.
The proposed method performance is developed for high-level synthesis (HLS) of datapaths in digital filters.
proposed strategy is developed for solving single and multi-objective issues.
Statistical and qualitative numerical result analyses assess the performance of the proposed method compared to other competitive algorithms.
The remainder of this paper is as follows: Th related works have been described in “Related work”. An overview about the Chimp Optimizer Algorithm (ChoA) are presented in “Chimp optimizer algorithm (ChoA)” respectively. “Problem formulation”, illustrates the all details of the high level synthesis (HLS) of the digital filters. “Modified SChoA version for high level synthesis of digital filters” describes the mathematical model of the proposed SChoA algorithm. “Results analysis and discussion of 23-standard test suites” and “Simulations and results of digital filters” presents the results and their analyses obtained by the proposed strategy and the competitor algorithms. “Conclusion and future work” concludes the paper.
MHAs recently are playing an most important role for digital filters issues. In fact, MHAs have provided extraordinary performances in several practical problems of a broad domain of applications, e.g., feature selection^11,12,13,14, optimization problems¹⁵, constrained engineering problems¹⁶, traveling salesman problems¹⁷, Case study Email spam detection¹⁸ respectively. For superior efficiency of the MA’s, various robust population based algorithms have been developed in the last few decades. This growing interest in population based algorithms coincides with the need for more efficient algorithms for finding the best solution’s of the complicated optimization functions. Some of these metaheuristic methods, including Genetic algorithms (GAs)¹⁹, Particle swarm optimization (PSO)²⁰, Henry gas solubility optimization (HGSO)²¹, Simulated annealing algorithm (SA)²², Archimedes optimization algorithm (AOA)²³, Cuckoo Search (CS) algorithm²⁴, Lévy flight distribution (LFD)²⁵ and Chimp optimizer algorithm (ChoA)¹⁰, One Half Personal Best Position Particle Swarm Optimizations (OHGBPPSO)²⁶, Personal Best Position Particle Swarm Optimization (PBPPSO)²⁷, Half Mean Particle Swarm Optimization Algorithm (HMPSO)²⁸, HAGWO²⁹, Hybrid Particle Swarm Optimization (HPSO)³⁰, HPSOGWO³¹, Hybrid MGBPSO-GSA³², HGWOSCA³³, MGWO³⁴, MVGWO³⁵, HSSAPSO³⁶, SChoA³⁷, HSSASCA³⁸, HSSAHHO³⁹, Hybrid Chimp-Cuckoo search algorithm (ChCS)⁴⁰, An enhanced chimp optimization algorithm for optimal degree reduction of Said-Ball curves⁴¹, Dynamic levy flight chimp optimization⁴², A weighted chimp optimization algorithm⁴³, Niching chimp optimization for constraint multimodal engineering optimization problems⁴⁴, Fuzzy-ChOA: an improved chimp optimization algorithm for marine mammal classification using artificial neural network⁴⁵, Optimization of constraint engineering problems using robust universal learning chimp optimization⁴⁶, Multi-Objective chimp Optimizer:An innovative algorithm for Multi-Objective problems⁴⁷, An enhanced chimp optimization algorithm for continuous optimization domains⁴⁸ and the SCA method was developed by Mirjalili et al.⁴⁹ for real world optimization issues. This algorithm is the most robust method for complex issues. It has played an important role in the modifications of the basis algorithm for presenting the new one enhanced methods. The SCA method has been designed by sine and cosine trigonometric functions. These functions play an important role for superior exploration and exploitation phases of the algorithm. The following mathematical formulations are applied in this method for finding the new one position in the search domain.
where (vec {x}_{i}^{t} ), (r_{1} ,r_{2} ,r_{3} in [0,1]) are illustrates the current position and random numbers and (l_{i} ) is targeted global optimal result. The above mathematical Eqs. (2.1)–(2.2) uses (0.5le r_{4} <0.5) setting for exploitation and exploration.
Recently, digital filtering is a big challenging optimization function. It is worth mentioning, that with the help of the robust nature inspired algorithms the various drawbacks of the digital filters have been resolved such as processing time and enhances the characteristics of the designed digital filters etc^50,51. Mohanty et al.⁵², have developed a distributed arithmetic approach for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. A new algorithm based on African vultures’ lifestyle is developed by Abdollahzadeh et al.⁵³. This strategy simulates African vultures’ foraging and navigation behaviors. The performance of this approach is verified through 36 standard test suites. Abdollahzadeh et al.⁵⁴ has presented the algorithm by gorilla troops’ social intelligence in nature, it is known as Gorilla Troops Optimizer (GTO). In this work, the gorillas’ collective life is scientifically framed, and new mechanisms are intended to execute exploitation and exploration. The robustness of the presented approach has been tested through 52 standard suites and engineering functions. A new approach that is stimulated through farmland fertility in nature is introduced by Shayanfar and Gharehchopogh⁵⁵, which has been assessed by utilizing the complex issues. In addition, the overview of Whale Optimization Algorithm, Spotted Hyena Optimizer, symbiotic organisms search algorithms and its applications is presented by Gharehchopogh et al.⁵⁶. Also, Luis and Arribas⁵⁷, have proposed a new approach for the design of digital frequency selective FIR filters using an flowers pollination algorithm (FPA), with a novel multiple fitness function, to get optimised filter coefficients that best approximate ideal specifications. Yadav et al.⁵⁸, applied grasshopper optimization algorithm (GOA) to design a linear phase finite impulse response (FIR) low pass, high pass, band pass, and band stop filters. proposed methodology target to reach minimum absolute error difference fitness function, through selecting optimal filter coefficients. In⁵⁹, the effectiveness of employing the swarm intelligence (SI) based and population-based evolutionary computing techniques is investigated for determining the optimal solutions to the FIR filter design problem.
The research of applying nature inspired algorithms to digital filters design has attracted much attention in last few years due to its utilization in a wide range of complex optimization functions⁶⁰. In general, digital filter is an optimization issue, in last few decades, regarding this issue various new strategies have been developed by the researchers for instance, such as; Lagos-Eulogio, Pedro, et al.⁶¹, have developed a new hybrid algorithm based on the combination of cellular particle swarm optimization (PSO) and differential evolution (DE) called CPSO-DE for the optimal parameter estimation of IIR digital filters. Wanga et al.⁶² have presented a novel design method that used a membrane computing method to design an optimal digital filter, their strategy that employed a tissue-like membrane system with ring-shaped topology structure. Panda et al.⁶³, have presented an IIR system identification using the cat swarm optimization (CSO). Wang et al.⁶⁴ have developed a framework called two-stage ensemble memetic algorithm (TSMA), TSMA employed to synthesize the strengths of the evolutionary global search and local search techniques. The proposed TSMA applied to design high-order digital IIR filters, experimental results compared to 6 state-of-the-art algorithms. Kaur et al.⁶⁵, have applied a new model to optimize the magnitude response and the phase response based on the greedy search method, binary successive approximation (BSA) and evolutionary search (ES) simultaneously, along with finding the lowest order of the filter. Kumar and Rawat⁶⁶ have employed cuckoo search algorithm (CSA), to get optimal coefficients of a fractional delay IIR (FD-IIR) filter, and to have an ideal frequency response characteristics. Upadhyay, P., et al.⁶⁷, have combined the Differential Evolution (DE) with Wavelet Mutation (DEWM) to IIR system identification problem. Also, to develop proper IIR filter designing method as a multi-objective optimization problem, Wang, Yu, Bin Li, and Yunbi Chen⁶⁸, have proposed a new local search operator enhanced multi-objective evolutionary algorithm (LS-MOEA). Saha et al.⁶⁹, have Presented a hybrid method of Gravitational Search Algorithm (GSA) and Wavelet Mutation (WM) called GSAWM, which applied on design of an 8th-order IIR filter, GSAWM target to achieve better cut-off frequency sharpness, smaller pass band and stop band ripples. Additionally, in⁷⁰, 2-dimensional IIR Filter design method based on hybrid PSO and SA is presented.
A novel population based method, is known as chimp optimizer recently originated by Khishe et al.¹⁰. The method is inspired by sexual motivation and individual intelligence of chimps. And it’s most famous for their group hunting. The hunting approach of this method is differ from the others. In this,strategy has used the four different phases such as driver, chaser, barrier and attacker respectively for searching the best score in the search domain.
All the working steps have been illustrated through the following mathematical formulations;
For chasing and driving the prey, has been used the following Eqs. (3.1)–(3.2);
where n illustrates the number of generations ,c,m and a are the coefficient vectors. These vectors c,m and a are evaluated through Eqs. (3.3)–(3.4)
where (r_1) and (r_2) are illustrated random values lying between (left[ 0,1 right] ), m is denoted the chotic vector and l has use for reducing non-linearly from 2.5 to 0 through the generation process. In this stage the behavior of the search agents has applied through mathematically. Firstly in the initial stage the each search member position is chosen by the given random values. In the next iteration, the first four best solutions are stored for updating the new position of the search member in the search domain. This procedure has been evaluated through the following mathematical Eqs. (3.6–3.9);
When the random values are lies amid (left[ -1,1 right] ), then the next position of the search member can be in any position amid its current location and the location of the target or prey.
As per all above mathematical formulations, the position of the search is evaluated by the Eq. (3.14);
At end, for position updating of each member has used following Eq. 3.15.
The pseudocode of ChoA is illustrated through Algorithm 1.
Retiming is a robust method for optimization which improves the sequential circuit performance. Generally, this method is applied for changing the positions of delay variables in a circuit without affecting the initial input and end outputs of the circuit. The brief details related of retiming are illustrates through the following subsections;
The main purpose of Retiming is transforming a digital filter graph to another digital filter graph by shifting the location of registers without moving the functionality of the circuits. Generally, it is used for reducing the delay variables count in the circuits. Because it could influence the clock period and delay variables, so it is obligatory to consider all phases into account. Additionally, it can be used to reduce switching operation which minimizes the dynamic power dissipation in circuits. A large amount of placing the component at the initial input node can reduce switching which plays a role for reducing power consumption. The main objective of retiming is to reduce the clock period. So, shifting the delay variable can be helpful in reducing the clock time period of a circuit.
If the transforms digital flow graph g to a retimed digital flow graph (g_{r}) then the final output or solution at the last is illustrates by a numerical quantity r(v) for all v. let w(e) and (w_{r}(e)) are illustrates the weight of the edge e in the first digital flow graph g be w(e) and in the retimed digital flow graph (g_{r}) be (w_{r}(e)). Finally, the weight at the each edge (uoverset{e}{rightarrow }v) in the retimed digital flow graph (grightarrow g_{r}) are evaluated by the following mathematical formulation;
where r(u) and r(v) are retime output vectors.
Retiming method is generally applied for the minimization of the CTP of the digital flow graphs. The least CTP for the digital flow graph, is the highest critical path computation time with no delay. The least feasible CTP, (phi (g)), is evaluated by the following mathematical formulation;
where (w(p)=sum _{i=o}^{n-1}(w(e_{i}))) and (t(p)=sum _{i=o}^{n}(v_{i})) are illustrates weight and computational time of the path. Further, through the following phases have been illustrated how to finds a retimining solution vector (r_{0}mid phi (g_{r_{0}})leqslant phi (g_{r})). Here w(u, v) and D(u, v) are used in retiming method to illustrates least number of delay and maximum computational time of the path from (urightarrow v).
In a digital flow graph (uoverset{e}{rightarrow }v), the edge weights are evaluated by the following equations;
where N and (I_{max}) are illustrates the number of nodes and maximum node execution time in digital flow graph.
In this phase, the following formulations are applied for deciding the next new shortest path in (uoverset{e}{rightarrow }v);
if (une v)
where (w(u,v)=leftlceil frac{s_{uv}}{m} rightrceil ).
if (u=v)
where (w(u,v)=0).
In this phase the CTP has evaluated by two matrices w(u, v) and D(u, v) over the following conditions of (left{ rmid phi (g_{r})leqslant CTP right} );
Feasibility constraint conditions;
Critical path (CP) constraint conditions;
where the feasibility condition is illustrate the delay variable on every edge non-negative and similarly, the critical path condition is to forces (phi (g)geqslant CTP). Similarly, if (D(u,v)>CTP), then (w(u,v)+r(v)-r(u)ge 1) should satisfy for CP execution time period (leqslant CTP).
In this phase, the algorithm is implemented for obtaining the retime vectors.
In circuit, if a single node has various output edges are connected to other nodes while the maximum delay variables needed for that output going edge is the highest delay variable of a single node. The brief details have been represented through the Fig. 1. These graphs are shows that here ’naive’ implementation shows (1+3+7=11) registers on Fig. 1 and ’clever’ implementation shows (max(1,3,7)=7) registers on Fig. 1. Similarly, with the help of following mathematical equation can be obtained the number of registers needed to apply the output edges of the node v in the retimed figure as:
where ( r_{v}) and (g_{n}) are illustrates the total register output cost in the retimed circuit and gadget node. Here, the above function holds under three different constraints or conditions as fanout, feasibility and clock time period respectively. These conditions or subject to constraints have been illustrated through the followings;
Fanout condition:
Feasibility condition:
Clock time period condition:
The graphs for fanout and clever implementation.
These retiming techniques would provide us with one maximal clock frequency solution. The designer would not be able to explore the entire potential solution space of the filter circuit under consideration. The entire solution space for the considered digital filters circuit is analyzed in the present evolutionary retiming algorithms and different feasible solutions are obtained. Depending on the critical path and the register count as the constraint, the designer can select any solution of his preference. Evolutionary algorithms explores the solution space by preserving all the node attributes of the digital filters graph. A framework model is generated to understand the design space for Pareto-optimal solutions. This will help the decision maker to converge at a design specification.
HLS is the process of converting a high abstraction level description of a design to register transfer level description. This is done by using MATLAB HDL coder that generates the synthesizable VHDL or Verilog code that has been executed to HDL work flow and generates the hardware design. This save the design cycle time with the generation of synthesizable report that gives information about the improvement in the speed and complexity reduction of the design with respect to novel retiming algorithm. The Matlab HDL coder and Xilinx tool transforms the specification into a register transfer level (RTL) implementation that can synthesize into a Xilinx field programmable gate array (FPGA). HLS techniques focus on design space exploration with reduced design cycle time and allow many optimization techniques and transformations. Herein this work retiming transformations are to be incorporated into the design for performance enhancement. The design space exploration results are taken from MATLAB and Viva do HLS. The retiming solutions in MATLAB are verified in Xilinx, along with clock period. Here the problem of optimally mapping a Data Flow Graph [DFG] specification of digital filters on to FPGA architecture has been done with the help of retiming transformation. This optimality is achieved using retiming based on meta heuristic algorithm(MHA). In this work, retiming based MHA algorithms are implemented on the different structures of the digital filters using HDL coder. A synthesisable RTL is obtained from input in which the location of the registers is altered in such a way that the overall clock period reduces, thereby increasing the clock frequency. This happens due to reduction in the critical path which bounds the speed of the design. Further, intelligent placement of registers is implemented that minimized the area. It is observed that the operating clock frequency in the digital filter can be increased to a great extent after novel approach.
Clock period and number of registers are considered as the optimization requirement in the present work. Using MHA, multiple retimed solutions are generated with high speed and different output register counts. Depending on the area constraint, user can choose the retiming solution with particular register counts. The MHA approach helps to find all possible retimed solutions and obtaining synthesizable HDL of the considered filter. For this, model is designed which automatically generates the synthesizable HDL of the considered filter. Again the choice of HDL (VHDL or Verilog) can be given by the user. This optimization environment reduces lot of design cycle time for the considered digital filters. The designer can choose any solution depending on the time units for critical path and the number of registers. With the designed environment, the designer can choose the required solution and can get the synthesizable HDL.
The sequential and recursive filtering of circuits is a complex optimization problem for the recent demand of the technology. The scientists are trying to solve this issue with the help of new one presented algorithms. However, each and every algorithm is not able to tackle these complex problems while these methods can be trapped in these types of complex issues. So, robust methods are required to resolve the complexity of these functions. According to present demand we are trying to present the new modified version SChoA for handling these complexities. This modified version is the mixture of two population based algorithms such as chimp and sine cosine methods. These trigonometric functions have been applied over the position update equation of the chimp optimizer for enhancing the exploitation phase. In addition, this enhancement, is developed for tackling various complex issues as slow diversity, premature convergence and slow convergence speed etc. Here all algorithms have been applied to solve the retiming issue as well as clock time period and area are the given constraints. Let v and (e_{ij}) illustrate the set of nodes and edges, where each edge is linked amid (i, j) vertices like (i ne j). In data flow graphs, delay is denoted the registers while linking nodes by an edge illustrated by weight vector (w_{ij}). The following three quantities are evaluates is the main prospectus of this implementation.
the least number of registers amid two paths on any path.
the least execution time required amid two paths on any path.
the high-level synthesis (HLS) of datapaths in digital filters.
In this stage, we are explain the implementation steps of the proposed method, that how to insert these digital filter functions with the proposed algorithm.
The main task of the proposed method that is minimize the fitness function t(l, m, r) for (t:goverset{e}{rightarrow }g_{r}). The subject to constraints as followings;
l: critical path
m: Registers
r: Total time required for evaluation
Also, find the output area of this issue to get all global retimed outputs. The many retimed outputs m created required to have;
Here the following cost function has been applied for calculating the global output given by (T(x)=left{ t_1(x),t_2(x),dots , t_m(x) right} ), where m illustrates the global outputs. The following mathematical formulation has been consider for optimization are
In this research the various population based methods have been runned parallel for fair comparison. During this implementation has been used thirty search members and five hundred maximum number of generations.
In the search domain the decision variable values of the given function are the same as the location of the search members of the population. The location of the each member of the crowd is assign as the following mathematical formulation (5.4);
Where n and d are illustrates the total number of search member in the search domain and dimension respectively. The fitness values of the each search member can be evaluate by the following mathematical Eq. (5.5);
where n and (fc_{i}) are illustrates the total of number search members and fitness outputs of the (i^{th}) member. Similarly, another two matrices can be formulate for the last node z (or target) of the graph by the following mathematical equations;
where n, d and (fz_{i}) are illustrates the number of nodes, dimension of the function and the fitness value of the ith node.
In this stage, the position of the search member in the search domain and distance of the given node is calculated by the following Eqs. (5.8)–(5.12), here these mathematical equations are illustrates the new location of the variable of the search member. Further, the Eqs. (3.1)–(3.5), are illustrates the distance b/w the position of the variable of the search member and the position of decision variables of the target.
For modified the location of the each member of the crowd in every generations with the aims of the improving the extractability of the proposed method has applied the following mathematical Eq. (5.13).
where (n_s),G and (M_{G}) are illustrates the number of search member, current iteration and maximum generations. Therefore, the search member of the crowd update their locations during the search process in the search area with respect to the target in the last generations.
The leader search member position modified by the following mathematical Eq. (5.14);
Lastly the following Eq. (5.15) has been used for updating the position of new path in the retimed data flow graph;
where (a_{s}) and (a_{t}) illustrate the updated location of new path by search member and location of the last node or target position.
The following fitness function⁷¹ has been applied for testing the best solution of the retiming problem with least cost path over the following subject to three different properties;
where R, M and (L_{max}) are illustrates the critical path, number of registers and longest path of the filter.
Here subject to constraints are hold over three different properties such as;
Prop-1: The weight (w) of the graph must be capable of rewriting as the weight (w) of the edge of the original graph, with the retimed value of each node. This can be mathematical formulate in the following form;
where (z_0) and (z_k) illustrate the start and end nodes in z of the retimed graph. The above mathematical formulation can be rewritten in the following form;
where v is represent the retimed vector.
Prop-2: In a retimed data flow graph (DFG), the weight (w) of the blocked way including the loop bound and repeated filing of this graph, should not exchange. In DFG the loop of a cycle is determined by the total time needed to run that particular circle. This is evaluated by summing up all nodes in the graph or cycle. And the generation bound illustrates the highest loop bound of every cycle in this graph.
Prop-3: The initial and last node of the edge in the data flow graph way would remain the same. This can be evaluated through the following mathematical equation;
If any output not fulfil these conditions would be the global output value with a given cost fitness function. We may penalize retimed output that do not fulfil the conditions with the value of the penalty that discharges these individuals during the selection process. The cost of the given function is evaluated in terms of number of registers and critical path after retiming. So, it is calculated by the above fitness function (5.16).
Lastly, the stopping criteria has been applied for updating the new one best path for the search member in the data flow graph. This process repeated again and again until it satisfies the criteria of prevention for example it reaches the highest generations or the output is earliest found.
The pseudocode of modified SChoA version is illustrated in Algorithm 2.
For evaluating the performance of the enhanced version has been used 23-standard test suites. These functions have been divided into three different phases such as 07-uni-modal, 06-multi-modal and 10-fixed dimension multi-modal test suites respectively. These test suites have been reported in the appendix table S1. The convergence performance and robustness of the enhanced algorithm have been compared with recent powerful optimizers such as Chimp, TACPSO, SCA and MPSO etc. Further, the analysis and discussions of the results have been illustrated in details in the following sub-sections:
All the evolutionary methods have been coded in the Matlab R2018a during the implementation. And algorithms have been runned on the system Intel(R) Core(TM) i3-8130U, RAM 8GB and Win 10. In these experiments have been applied different constant settings such as 30-number of search agents and 500- number of iterations respectively. It is constantly advantageous to use a standard test suite with dissimilar features to suitably and assertively verify the robustness of MA’s on altered standard test suites and compare it with recent MA’s. The diversity of these test suites permits detecting and analyzing the capability of the proposed method from dissimilar standpoints. In uni-modal test suites have only one global optimum with no local optima. Generally, these test suites are highly suitable for comparing the convergence and exploitative ability of the MA’s. Additionally, the multi-modal and fixed dimension multi-modal test suites face the survival of numerous local optimum outputs and more than one global optimum.
Here, the 23-test suites have been used to validate the robustness and efficiency of the enhanced version compared to with others recent MA’s. These test suites have been divided into three categories such as uni-model, multi-modal and fixed dimension multi-modal functions. These test suites have been illustrated through appendix table S1.
The performance of the algorithms have been tested on 23-test suites and experimental results are illustrated in the table. The robustness of the algorithms have been verified in terms of best minimum cost, maximum cost, average and standard deviation etc. Here the least and maximum cost of the fitness test suites illustrates the best performance of the evolutionary algorithms. And the statistical outputs have also been used for testing the robustness of the algorithms. All these results have been computed at the last iteration for every evolutionary algorithm on every test suite to get the best global optima solution, to compare meaningful best outputs.
Firstly, the performance of the evolutionary algorithms have been tested on uni-modal test suites (F1–F7). Generally, these test suites are applied to evaluate the exploitation phase. The results of algorithms on these test suites have been illustrated through Tables 1, 2, 3 and 4. All the results of these tables gives strong evidence that the enhanced algorithm has been able to provide the better exploitation ability as compared to others. As mentioned earlier, these standard test suites are most suitable for these functions. Experimental outputs prove that the SChoA algorithm is highly functional. Furthermore, these experimental solutions prove that the proposed strategy can be highly effective and robust in giving the accurate and best optima for the high complex space test suites as compared to others.
Further, the performance of the evolutionary algorithms have been verified on multi-modal ((F_8)–(F_{13})) and fixed dimension multi-modal ((F_{14})–(F_{23})) test suites. The all results of algorithms on these test suites have been illustrated through Tables 1, 2, 3 and 4. These test suites have many local and the number of decision variables increases exponentially with the size of the test suite compared to the uni-modal test suite. Generally, these test suites are used to assess the exploration ability and suitability of the evolutionary algorithms. All results of tables, shows that the enhanced strategy achieves a higher detection ability and superior exploitation ability.
In this subsection, the average scores obtained by the evolutionary algorithms on 23-test suites have been discussed briefly in the Table 2. The average values have been divided into two categories like worst average score (W) and best average score (B) etc. Generally, the least average score denotes the accuracy of the evolutionary algorithms for the best outputs. In the Table 2, we can see easily that the proposed strategy is able to find the best optima solutions in at least average scores for the maximum standard test suites in the highly complex space. Hence these results give strong evidence that the proposed strategy can find the accurate solutions for the highly complex test suites as compared to others.
The standard deviation is used to verify the solution stability of the evolutionary algorithms. In this phase, the performance of the evolutionary algorithms have been discussed on the behalf of statistically. The standard deviation values obtained by the evolutionary algorithms on the 23-test suites have been plotted through Fig. 2. In this graph, we can see easily that the standard deviation values of the proposed strategy on 23-test suites are near to 0, it means that the proposed strategy is stable on the test suites that were performed. Additionally, the least standard score shows the best convergence performance of the evolutionary algorithms. Hence, here, it can be concluded that the proposed methodology can able to fastly trap the best global optima solution in the search space as compared to others.
The standard deviation (SD) values of evolutionary algorithms on 23-standard test suites.
In this phase we are discussing the convergence performance of the evolutionary algorithms on 23-test suites. All these graphs have been plotted through Figs. 3, 4 and 5. In this graph the x-axis and y-axis are denoted the number of iterations and best solutions respectively. These graphs show the evolutionary algorithm how much takes a number of iterations or time for finding the best score in the search space during the search process. Additionally, as per Berg et al.⁷², this behavior can assure that evolutionary methods ultimately converge to a point and are found locally.
So, being these reasons, we can discuss and as per reasoned to the proposed methodology. The search members move from high score to low scores, so with the assumption of growth in proposed methodology, the overall chimps and their fitness are improved during the iterations. With this methodology, we save the best score for finding the next one best score and this value helps the search member during the search process in the search space for searching the next best score. On the basis of these graphs, we can conclude that the proposed strategy is able to trap the best score in least numbers of generations or time as compared to others. And could be capable of resolving very complex issues easily.
The convergence graph of algorithms on 07-Uni-modal test suites.
The convergence graph of algorithms on 06-Multi-modal test suites.
The convergence graph of algorithms on 10-Fixed dimension multi-modal test suites.
Here, the proposed method have demonstrated their efficiency and capability over traditional optimizers for generating the topology, rules and optimal parameters that deliver the superior classification performance with concerning to the quality of the global result, avoiding local minima and computational cost. So,the proposed method can be more helpful for addressing the complex domain issues and new Challenges.
In this work, an enhanced version of chimp optimizer have been applied on 14- different data filters such as DF-FIR, LATFIR, CASFIR, PARFIR, TDFFIR, DF1IIR, TDF1IIR, TDF2IIR, DF2IIR, CASIIR, SLATIIR, DLATIIR, PARIIR and LADIIR for evaluating the several outputs. Under designing the complex filters high level synthesis is a large paramount stage for that. Generally, the high-level optimization methodology has been applied for reducing the designing period time at the lower levels, leading to superior circuit indices⁷³. In this work is synthesized using MATLAB HDL coder and Viva do HLS. All the benchmarks are synthesized on the Virtex family in term of maximum usable frequency, Critical path delay and no of slices utilized in term of flipflps, LUTs, no of DSP slices etc. Other HLS tool available in the market are Stratus HLS from Cadence, HDL coder from MATLAB, Intel FPGA, Viva do HLS from Xilinx.
During implementation, Matlab HDL coder is preferred. It generates synthesizable VHDL code from MATLAb , Simulink models. The HDL coder provide the workflow advisor that automates the program that be used for programming for Xilinx. The Xilinx High-Level Synthesis (HLS) compiler provides a programming environment similar to those available for application development on both standard and specialized processors. The programming model of an FPGA was centered on register-transfer level (RTL) descriptions which illustrates how the programming model difference affects implementation time and achievable performance for different computation platforms. During this methodology, the number of registers can exceed which may be the constraints to the designer. Here, we are trying to present the superior quality of solution for these issues. The various recent algorithms and modified algorithms have been applied for verifying the accuracy of the solutions of this issue. The matlab code of all the algorithms have been runned over the system with Intel (R) Core (TM) i3-8130 U processor and 8GM of RAM. In this implementation the various parameter values applied like number of search agents (30) and number of 500 iterations respectively.
The numerical solutions of the digital filters have been reported in Tables 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 and 34 in the terms of least minimum, highest maximum, average, standard deviation, execution time, occupied area and speed respectively. The performance of the algorithms have been illustrated over single and multi-objective functions. Under this study have been considered two categories of functions for evaluated the high level synthesis of the digital filters such as (1) 14-single objective digital filters and (2) 14-multi-objective digital filters. In Tables 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, have illustrated the performance of the algorithms on the 14-single objective digital filters. The numerical solutions in these tables shows that the proposed method gives the best score as comparison to others. In Figs. 6, 7, 8, 9 and 10 of these filters also proven that the proposed algorithm is able to provide the best optima and accurate solution in the least time and in the least number of iterations or runs. So, the proposed algorithm can be able to prove its own efficiency to reduce the complexity of these filters.
The convergence graph of algorithms on single-objective DF-FIR, LATFIR and CASFIR digital filters.
The convergence graph of algorithms on single-objective PARFIR, TDFFIR and DF1IIR digital filters.
The convergence graph of algorithms on single-objective TDF1IIR, TDF2IIR and DF2IIR digital filters.
The convergence graph of algorithms on single-objective CASIIR, SLATIIR and DLATIIR digital filters.
The convergence graph of algorithms on single-objective PARIIR and LADIIR digital filters.
The graph of execution time of algorithms on single-objective digit filters.
Similarly, in Tables 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, have been reported the algorithms solutions on the multi-objective digital filters. The outputs of the algorithms are revealed that the proposed method is capable of presenting the best and accurate global optima solutions on these multi-objective functions. The convergence performance of the algorithms have been plotted through the Figs. 12, 13, 14, 15 and 16. These graphs give the proof of the best solutions trapping performance of the algorithms. And proven that the proposed method easily and quickly trapping the best and accurate global solution with the least number of iterations and time.
The convergence graph of algorithms on multi-objective DF-FIR, LATFIR and CASFIR digital filters.
The convergence graph of algorithms on multi-objective PARFIR, TDFFIR and DF1IIR digital filters.
The convergence graph of algorithms on multi-objective TDF1IIR, TDF2IIR and DF2IIR digital filters.
The convergence graph of algorithms on multi-objective CASIIR, SLATIIR and DLATIIR digital filters.
The convergence graph of algorithms on multi-objective PARIIR and LADIIR digital filters.
In Tables 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, the execution time of the algorithms on the single and multi-objective digital filters have been illustrated. The results show that the proposed algorithm can be trapping the best global optima solution in the complex search domain easily and fastly outperforms others. The execution time performance of the algorithms on the single and multi-objective digital filters have been plotted through Figs. 11, 12, 13, 14, 15, 16 and 17. These graphs give strong evidence that the proposed method is able to trap the best goal fastly as comparison than others.
The graph of execution time of algorithms on multi-objective digit filters.
The average values of the algorithms have been illustrated through a Fig. 18. This graph has been plotted over the average values of the algorithms on the multi-objective digital filters, these values are shown in Tables 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33. Generally, the least value of mean represents the accuracy of the optimizer algorithm for the best global optima. These figures give strong evidence of the superior accuracy of the proposed algorithm as comparison with others on these multi-objective digital filters. Finally, we can say that the proposed methodology is able to present accurate and superior global optima solutions for these complex filters.
The average values of the proposed algorithm on 14-multi-objective digital filters.
In this phase, we are discussing the standard deviation values (sd) of the algorithms. The sd values of each algorithm have been plotted by the graph or Fig. 19 with respect to x-axis and y-axis respectively. These values are illustrates through Tables 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33. Generally, these values near to zero represent the stability and fast convergence performance of the algorithm. This graph gives strong evidence that the proposed methodology all standard deviation results are near to zero which presents the proof of global optima solution stability and fast convergence performance of the proposed method outperform than others. Here, we can conclude that the proposed method is able to trap the best global optima with least number of iterations and time as comparison than others.
The standard deviation values of the proposed algorithm on 14-multi-objective digital filters.
This paper has proposed a novel approach based on the recent meta-heuristic algorithm of SChoA. After using this approach in digital filter synthesis, it was found that, relative to other approaches, the proposed process has a greater ability to achieve optimal solutions in the same initial state (the initial population and the same number of iterations). In our suggested method, SChoA algorithm was applied separately to each node, where the location is modified according to the retiming strategy to which the SChoA algorithm is applied. In this way, the SChoA algorithm is applied to all the nodes available on the path. This enables the proposed algorithm to solve the current restrictions of identifying operator execution quickly and accurately. Lattice Ladder IIR filter system is taken into the account as an example to evaluate different outcomes using evolutionary algorithms based retiming approach. By significantly reducing the longest activities in a retimed DFG, the clock performance increases. It is by lowering while using this as next critical path in the system. The count of registers will rise in the process that could be the designer’s limit.
SChoA, MFO, PSO are highlighted here as the evolutionary algorithm based on Pareto, although there are other algorithms available on Pareto that may be considered for comparative analysis. The results of the algorithms have been illustrated in Table 35. In the entire solution space, the decision vectors that are not dominated can be represented as optimal Pareto and entail an optimal Pareto front. The Pareto front has been shown in two dimensions (Path delay and number of registers) to manipulate the objectives. The Pareto fronts identified using the information gathered for the analysed filters from the objective solution space are shown in the Figs. 20, 21, 22, 23 and 24 where the blue line indicates the relevant information obtained by the proposed process, while the red line reflects the algorithm data based on the MFO and the green line shows the algorithm-related data based on the PSO. In addition, the number of registers has been used in the vertical axis to clearly represent the data, which provides a clearer comparison of the three methods. In the Lattice Ladder IIR filter, the most appropriate solution fulfilling the goals is with a clock period of 5 time units and register count of 11. Besides that, even if clock period is chosen a limit, then with clock period as 3 and register count as 14 from the search space can be considered. From the design space if register count is a constraint, then response with clock time as 5 and register count as 11. An entry into the potential solution space would come from the one that does not alter the circuit functionality. This process will proceed until all feasible solutions are obtained. The designer may select either solution refers to a time units for critical paths and the registers count.
Consequently, the findings certainly showed selection in view of register and path latency, leading to an improvement in the design stage of the filters for the optimum solution. The solution space that provides the path lower than the initial critical path that fulfils all the retiming features is calculated by all feasible routes from the source node to the destination node. In the DLAT-IIR, the Pareto set at a path delay of 3 time units and a register count of 6 is the most suitable option that meets both objectives. However, if only a path delay is considered a restriction, the solution can be interpreted as a path delay with 3 and register 10 as a register count. For the register count as a restriction, another approach in terms of path delay as 5 and register count as 6. A 37.13%, 30.18% improvement in the MUF and area, 39.74% and 40.51% in relative to MFO, PSO based algorithms. The pareto optimal front for the consideration of 14-digital filters are shown in Figs. 20, 21, 22, 23 and 24. The retimed best optima results have been evaluated during this work for the single and multi-objective digital filters. Generally the search domain is finalized at each path from initial node to final node which provides the path less than the critical way that fulfills all the given conditions or properties.
The pareto graph of algorithms on multi-objective DF-FIR, LATFIR and CASFIR digital filters.
The pareto graph of algorithms on multi-objective PARFIR, TDFFIR and DF1IIR digital filters.
The pareto graph of algorithms on multi-objective TDF1IIR, TDF2IIR and DF2IIR digital filters.
The pareto graph of algorithms on multi-objective CASIIR, SLATIIR and DLATIIR digital filters.
The pareto graph of algorithms on multi-objective PARIIR and LADIIR digital filters.
The information obtained through the simulations of the three methods are listed in the tabulated form, i.e. SChoA-Proposed Method, MFO-based Method, PSO-based Method. In all the methods, the initial population and the maximum number of iterations are equal to 30 and 500. The results of the HLS of the digital filters have been tabulated in Table 36 where the maximum frequency available and the occupied area, that is the number of slices register used for the implementation of the operators and registers.
Table 37 summarises the percentage of the improvement achieved by the proposed SChoA-based method than other methods (MUF-based and PSO-based) while synthesising each digital filter. Table 37 clearly illustrates that in the DF-FIR, the current method have significantly improve MUF by 26.70% and 38.13% as compared to the MFO-based and PSO- based method. And the proposed method have provided improved MUF by 61.29% compared to the PSO-based method for DF2IIR. And compared to the MFO-based and PSO-based methods, the proposed method used fewer slices. For the optimum frequency, the proposed method in LAT FIR, DLATIIR filters synthesis revealed the best compared to the MFO-based, PSO-based, with 21.05%, 25.51% and 37.13%, 30.18% improvement. The best outcome for utilized slice registers was observed in the DF-FIR synthesis, with an improvement of 59.70% compared to the PSO-based method and an improvement of 39.74% in the DLAT-IIR synthesis compared to the MFO-based method. Important improvements have been identified in the Tables 36 and 37 to reach an optimal solution in terms of throughput. Our proposed method outperformed the other two with respect to two parameters (MUF and Area) for the filter synthesis. In Table 38, have been compared the execution time taken by the evolutionary algorithm for the 14- different digital filters. The results of this table give strong evidence that the proposed algorithm is able to tackle these issues in least time as comparison with others.
By comparing the performance of models, it would be reported that the optimum operating frequency for Lattice Ladder IIR filter has enhanced from 17.884 to 28.186 MHz that is improved by 57.6% whereas the number of slices used get declined by 23.52%. From the statistic it has been seen that the proportion of latches does get controlled well with desired clock period for the evolutionary retiming algorithm. For the performance analysis which including area and delay, models are evaluated and HLS has been used to optimize register transfer logic. The improvement in the clock rate of FIR and IIR digital filters during novel retiming algorithm are shown in Table 37. It highlights that after implementing the novel approach, the stepladder of the different arrangements are whittled down. The declination of the register count accelerates the design’s clock rate and trim down the feature size that further enhances performance level. Summing up, on the basis of all simulations, we concluded that the proposed methodology can tackle the complex digital filters issues strongly.
Under this phase, the proposed strategy has been implemented on the high level of synthesis. HLS (high level synthesis) is a paramount phase during designing the digital filters. Normally, HL optimization decreases design period at minor stages, foremost to superior circuit indices⁷³. HLS is a platform of very big scale integration (VLSI) design where in behavioral explanation is transformed into a physical representative^76,77. The HLS is the initial stage in synthesizing a circuit and data flow graph (DFG) is utilized to illustrate the behavioral explanation, which defines the operators’ type and the connections amid them. The assumed DFG has been demonstrated by the Eq. (7.1);
The digital filters (DF’s) are commonly utilized for videos, process signals, images, communication applications, digital signal processing etc. The auto regressive filter (ARF), finite impulse response (FIR), the band-pass filter (BPF), the infinite impulse response (IIR), the elliptic wave filter (EWF) and the wave digital filter (WDF) are the DF’s used in this work. The DFG of the ARF used in this text has been demonstrated by Fig. 25⁷⁸.
The ARF data flow graph.
The following fitness function has been considered for evaluating the area, power and delay by the proposed strategy and verify the accuracy by the results of MFO⁷⁴ and PSO⁷⁴ algorithms:
where F is illustrated the fitness function, (w_{1}),(w_{2}),(w_{3}) are describes the weights of the power, delay and area terms, (l_{t}) is represented the schedule length of sample evaluated, (a_(t)) is illustrated the total number of registers and transistors in the operators, (p_{t}) is denoted the power consumption of operators, (l_{max}) is denoted the long scheduled length in the current crowd,(a_{max}) is denoted the largest area in the current crowd and (p_{max}) is denoted the highest power in the current crowd respectively.
The best outcomes for delay, occupied area and power in HLS of digital filter issues.
Further accurately illuminates on the best optima results attained by the newly proposed method in the subsequent period of this subdivision. These outcomes have been confirmed over the recent literature solutions achieved by MFO⁷⁴ and PSO⁷⁴. The code of the algorithms have been runned on Matlab-R2015a under the system with 8GM of RAM and Intel (R) Core (TM) i3-8130 U processor. The various constants values have been fixed for getting the best outcomes viz total no ’s of search members are 30, total no’s of generations are 100, total no’s of operational units and sources are 5 etc. The experimental outcomes of the HLS of the digital filters have been described through Tables 39, 40, 41, 42, 43, 44. Similarly, the best outcomes of the newly developed approach for power, occupied area and lowest delay are presented by Fig. 26. All outcomes have assessed on three modes such as (w_1=0.8), (w_2=1),(w_3=1) and (w_1=1), (w_2=0.8), (w_3=1) and (w_1=1), (w_2=1), (w_3=0.8) etc. For every mode, the average of the assimilated reaction for a 50-times effecting for the newly developed approach has been tabulated beside with their appropriate the standard deviation(sd). Here keep in mind that, the standard scores (sd) have been reported for a comparison and superior presentation of the result with respect to the power consumption and largeness of the occupied area.
The outcomes of Tables 39, 40, 41, 42, 43, 44, shows that the proposed method is able to give a highly accurate and superior outcome in terms of area, power and delay than others. All outcomes of IIR, FIR, ARF, EWF, BPF and WDF-DFG have been attained through changing the constant values of ((w_1), (w_2), (w_3)) and a major improvement in the global optimal outcome responses of the MA’s observed. For illustration, the best delay will be attained, linked to the other two modes, when supposing a weight of 0.8 for (w_{1}), this factor is associated to the delay, and supposing a coefficient of 0.1 for (w_{2}) and (w_{1}) as the coefficients of the occupied area and power. The same is true for the other two modes. All least scores in Tables 39, 40, 41, 42, 43, 44 of the newly developed algorithm revealed are able to give the highly effective and accurate solutions for the occupied area and the least power consumption than MFO⁷⁴ and PSO⁷⁴ algorithms. In addition, the outcomes of Table 40 proved that the mean scores for the delay have been attained by the new method in comparison to others. These outcomes revealed that the new method is capable of decreasing the delay period than other for HLS issues. Therefore, the new strategy is competent to deliver the paramount outcome response in terms of delay, area and power consumption for HLS in VLSI circuits.
Summing up, the performance of the proposed algorithm shows that it is able to provide the high quality of the global optimal solutions outperforming the original algorithms. The powerful features of the proposed method can deal with the NP-hard applications of different domains. So this approach would be helpful in handling complex real-world problems.
In the paper, a enhanced version of chimp optimizer with sine cosine functions have been designed for the high level synthesis (HLS) of digital filter data-paths in terms of best score, execution time, occupied area and speed. The sine and cosine functions are helped of the algorithms in fluctuating toward or outward searching the global optima solutions. These functions are also able in ignoring the local optima and forcing for trapping the global optima fastly in the search domain. The performance of the algorithms have been tested on 23-standard test suites and 14-different digital filters of single and multi-objective functions in terms of minimum, maximum, average, standard deviation, execution time, occupied area and speed. The simulation results of the proposed strategy shows that the proposed strategy is able to successfully solve the high level synthesis of datapaths in digital filters problem in terms of area and speed respectively as comparison than to others. It is also able to trap highly accurate global optima solutions in the search area with least number of iterations and time than others.
Further, for the SChoA evolutionary algorithms, maximum improvement analysed in the frequency, the occupied area for DR- FIR is 38.13%, 59.70% and for DF2-IIR is 61.29%, 15.69% ,for LAT-IIR is 52.37% , 14.67% and also for LAD-IIR is 43.95%, 59.07%. This could greatly reduce the cost of systems with broad dimensions while increasing the design speed. Practically, the entire framework is saving the designer resources and time. In addition, the SChoA is competent to effectively solve the HLS of datapaths in digital filters issue in terms of lowest delay, area and power respectively than others. In future work, we shall develop the various enhanced versions of the algorithms for the high level synthesis and model identification of the digital filterings. In the end, we expect this work will encourage the young scientists of different domains, who are recently working on MA’s and digital filtering issues.
All data included in this study are available upon request by contact with the corresponding author.
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Department of Electronics and Communication Engineering, Punjabi University, Patiala, India
Mandeep Kaur & Ranjit Kaur
Department of Mathematics, Punjabi University, Patiala, India
Narinder Singh
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Kaur, M., Kaur, R. & Singh, N. Enhanced chimp optimization algorithm for high level synthesis of digital filters. Sci Rep 12, 21389 (2022). https://doi.org/10.1038/s41598-022-24343-x
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Received: 20 June 2022
Accepted: 14 November 2022
Published: 10 December 2022
DOI: https://doi.org/10.1038/s41598-022-24343-x
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